1. Technical Field
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device having a junctionless vertical gate transistor and a method of manufacturing the same.
2. Description of the Related Art
The design rule margin has been decreased with an increase in the degree of integration of semiconductor devices. Such decrease in design rule margin results in limitations on the technical development of high density semiconductor devices.
In recent years, studies have been focused on development of a 4F2 layout (F; minimum pattern size obtainable under a given process condition), which permit formation of cells with a remarkably higher density. Particularly, vertical channel transistors where a source and a drain are formed in 1F2 have been studied.
However, as a channel region is reduced to 30 nm or less, it becomes more difficult to improve the degree of integration due to a process difficulty and an increase in leakage current resulting from a size reduction of semiconductor devices.
For example, Korean Patent No. 0784930, herein incorporated by reference, discloses a memory cell having a vertical channel double gate structure, which has an active region of an NPN junction structure.